What Is RISC-V and Why It Will Be the next Big Thing for Wearables?

One of the major components inside a smartphone or any device, is the System on a Chip, or as we say in general terms, a “Processor” or a CPU, in the case of personal computers. From Intel’s first-ever processor, the 4004, to one of the most popular processors of its time, the Intel 8006, there have been rapid developments in instruction set architectures including both the CISC and RISC instruction sets used by Intel/AMD and ARM, respectively. And now, there’s a new kid in town (Well, RISC-V is quite old and was founded in 2010. It’s still relatively new compared to ARM, though). Here’s everything you need to know about RISC-V and why it’s so important for not just Android and WearOS but Qualcomm and many other investors in the same.

What is RISC-V?

RISC-V, pronounced “risk five,” is an Instruction Set Architecture (ISA) like ARM and RISC, but unlike them, it’s completely license-free and open-source. For starters, think of instruction set architecture as a medium that connects hardware and software. It defines and dictates the way both hardware and software work to produce results, i.e., the result a user wants. It could be a press of a button in a UI or passing complex instructions while playing a game.

RISC-V ISA is flexible and more efficient, and one of the main reasons why companies are invested in it is because it’s open-source and doesn’t require them to pay licensing fees.

Now, given the name “RISC-V” you may think of it as a sort of successor to RISC and no, that’s not true. RISC is proprietary and is used by ARM to hand out instructions to companies such as Samsung, Qualcomm, and Apple. They get to use those “instructions” to make their own SoCs. RISC-V, on the other hand, involves no middlemen. It’s completely free, and open-source, which means companies can take the instructions without paying huge licensing fees like they would to ARM, and start building a processor on the RISC-V ISA.

Since the ISA is open-source, like with any open-source software, RISC-V International is always looking for ways to improve the code and make it more efficient. Although, one of the things worth mentioning is that, RISC-V is license-free but companies can take it and make it closed-source since they can do that. It’s more or less a similar situation to that of Android where AOSP is completely free (although Google asks OEMs to pay a licensing fee for Google Apps) but companies build on AOSP and don’t reveal the source code of their UIs.

RISC-V vs RISC vs CISC

Both RISC and RISC-V are Reduced Instruction Set Computer which is found in devices with smaller SoCs like smartphones, but the same has also been expanded to computers (M1 Macs, Qualcomm’s X Elite Platform). CISC stands for Complex Instruction Set Computer and is used by processor manufacturers such as Intel and AMD.

The main difference between RISC-V, RISC, and CISC is, that RISC-V and RISC are Reduced Instruction Sets with the former being completely free and open-source and the latter being proprietary, whereas CISC is where the ISA completes complex instructions to solve an activity. RISC is where the ISA completes a large number of small instructions to complete a task.

An example of CISC is x86 and x86-64 from Intel and AMD. We’ll leave the explanation about their history for another article but all you need to know is, that x86 and x86-64 processors require more power, and aren’t as efficient as RISC ISA, but are quite powerful. Although the line between RISC and CISC has blurred in recent years, CISC is still more widely used in personal computers and for industry purposes than RISC; however, RISC is slowly getting there (Apple’s M1 processors anyone?).

Why RISC-V? What are the Advantages?

One of the obvious advantages of RISC-V for companies such as Google and Qualcomm is that it’s completely free and open-source so they don’t need to pay anything. Besides, here are a few advantages on the consumer side that will be beneficial to both consumers and manufacturers.

  • Increased security. Being open-source means security flaws can be addressed very quickly.
  • Improved software updates since the ISA is common across all manufacturers.
  • Better performance and efficiency from the SoCs thanks to the rapid development and improvements that come from being open-source.

The other major reason why we need RISC-V is to address ARM’s monopoly and future licensing issues. You see, ARM has recently started bumping the prices of its licensing fee leaving manufacturers with no choice but to pay the same since there’s nothing else that they could jump to. Another event that sent shockwaves in the industry was when NVIDIA tried to acquire ARM. This made the industry giants question if NVIDIA would stop licensing the ARM ISA to others, which, considering it’s NVIDIA, was very much plausible. This made companies invest in the development of RISC-V and lead the next generation of connected platforms by giving it a significant boost monetarily and by kickstarting hardware development.

Another significant problem that RISC-V solves is related to trade barriers. If you work in Tech, you may have seen lots of news around the USA banning Huawei and then China doing the same, for whatever reasons. RISC-V is completely free, not just from the trade hurdles but also from the clutches of any country because it’s based in Switzerland.

How will RISC-V Benefit Google and Qualcomm?

Well, a lot of things. First up, Qualcomm would have to pay zero fees and will probably completely switch to RISC-V in the near future, across all its products for smartphones, IoT, and general connected tech. In recent events, Qualcomm and Google will be collaborating to make RISC-V-based processors for Google’s wearables (Pixel Watch and Fitbit) and hopefully for Pixels down the line (Get rid of Tensor Google, please!). We believe that the processors will first show up in Google’s Fitbit range.

Earlier this week, Google posted an update for Android on RISC-V and how the giant has been working to bring its WearOS and other platforms on RISC-V. The video in the post included Android booting up and running on a RISC-V processor. While AOSP (Android Open Source Project) isn’t fully optimized yet, Google claims that emulators will be made available for public use by 2024.

Given the advantages of RISC-V, Google can push more updates (Although 7 years on the Pixel 8 already seems like an overkill, but is great nonetheless), and improve the overall performance and battery life of its wearables. Some of the initial RISC-V vs RISC test results look promising, but RISC-V still clearly has a long way to go.

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