In an earnings call with investors last week, Taiwan Semiconductor Manufacturing Company (TSMC) shared the initial details about its 3nm (N3) process node that’s expected to become operational next year. According to the company’s CEO, C.C. Wei, risk production for N3 chips remains on track for 2021 despite the pandemic and associated disruptions in production. Volume production of 3nm chips, however, is only set to commence in the second half of 2022, he said.

The 3nm node will make use of FinFET technology because of its maturity, reliability and cost-efficiency. Wei also claimed that the N3 will have a density improvement of 1.7x over N5 (5nm process node), while estimates provided by WikiChip suggests the former should offer a cell-level density of just under 300 million transistors per square millimeter. In terms of performance and speed, TSMC claims that N3 will provide 10-15 percent speed improvement over N5 at iso-power or 25-30 percent power reduction at iso-speed.

The first concrete news about TSMC’s 3nm technology comes almost exactly a year after the company’s 5nm node entered risk production last year. According to Wei, N5 production is now being ramped up with good yield. It is expected to deliver around 1.8x improvement in density along with 15 percent higher speed at iso-power or, alternatively, 30 percent lower power consumption at the same speed over N7.

The company expects N5 to contribute about 10 percent of total wafer revenue in 2020 even as its flagship 7nm process node continues to remain the top dog in the foreseeable future. In the first quarter, N7 contributed around 35 percent of the company’s revenues, while both 16-nanometer and 10-nanometer revenue share dropped marginally because of weaker demand for older SoCs.

SOURCEWikiChip

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